View LH5324P00A_255733.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

PRELIMINARY
LH5324P00A
FEATURES * 3,145,728 words x 8 bit organization (Byte mode) 1,572,864 words x 16 bit organization (Word mode) * Access time: 120 ns (MAX.) * Power consumption: Operating: 440 mW (MAX.) Standby: 1650 W (MAX.) * Static operation * TTL compatible I/O * Three-state outputs * Single +5 V power supply * Package: 44-pin, 600-mil SOP DESCRIPTION
The LH5324P00A is a 24M-bit mask-programmable ROM organized as 3,145,728 x 8 bits (Byte mode) or 1,572,864 x 16 bits (Word mode) that can be selected by a BYTE input pin. It is fabricated using silicon-gate CMOS process technology.
44-PIN SOP
CMOS 24M (3M x 8/1.5M x 16) Mask-Programmable ROM
PIN CONNECTIONS
TOP VIEW NC A18 A17 A7 A6 A5 A4 A3 A2 A1 A0 CE GND OE D0 D8 D1 D9 D2 D10 D3 D11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A20 A19 A8 A9 A10 A11 A12 A13 A14 A15 A16 BYTE GND D15/A-1 (LSB) D7 D14 D6 D13 D5 D12 D4 VCC
5324P00A-1
Figure 1. Pin Connections for SOP Package
5-307
LH5324P00A
PRELIMINARY
CMOS 24M Mask-Programmable ROM
A20 44 A19 43 A18 2 A17 3 A16 34 A15 35 A14 36
ADDRESS BUFFER
DATA SELECTOR/OUTPUT BUFFER
A13 37 A12 38 A11 39 A10 40 A9 41 A8 42 A7 4 A6 5 A5 6 A4 A3 A2 7 8 9
ADDRESS DECODER
MEMORY MATRIX (3,145,728 x 8) (1,572,864 x 16)
31 D15 29 D14 27 D13 25 D12 22 D11 20 D10 18 D9 16 D8 30 D7 28 D6 26 D5 24 D4 21 D3 19 D2 17 D1
COLUMN SELECTOR
A1 10 A0 11
CE 12
CE BUFFER
TIMING GENERATOR
15 D0 SENSE AMPLIFIER
OE 14
OE BUFFER
BYTE 33
BYTE/WORD SWITCHOVER CIRCUIT
ADDRESS BUFFER
31 A-1
23 VCC
13 32 GND
5324P00A-2
Figure 2. LH5324P00A Block Diagram
PIN DESCRIPTION
SIGNAL PIN NAME NOTE SIGNAL PIN NAME NOTE
A-1 - A20 D0 - D15 BYTE CE
Address input Data output Byte/word mode switch Chip Enable input
1 1 1
OE VCC GND NC
Output Enable input Power supply (+5 V) Ground No connection
NOTE: 1. The D15 /A-1 pin becomes LSB address input (A-1) when the BYTE pin is set to be LOW in byte mode, and data output (D15) when set to be HIGH in word mode.
5-308
CMOS 24M Mask-Programmable ROM
PRELIMINARY
LH5324P00A
TRUTH TABLE
CE OE BYTE A-1 (D15) DATA OUTPUT D0 - D7 D8 - D15 ADDRESS INPUT LSB MSB SUPPLY CURRENT NOTE
H L L L L
X H L L L
X X H L L
X X - L H
High-Z High-Z D0 - D7 D0 - D7 D8 - D15
High-Z High-Z D8 - D15 High-Z High-Z
- - A0 A-1 A-1
- - A20 A20 A20
Standby (ISB) Operating (ICC ) Operating (ICC ) Operating (ICC ) Operating (ICC )
1 1
NOTE: 1. X = H or L; High-Z = High-impedance When the address inputs become 'High' to both A19 and A20, the data outputs become `Unspecified' since the data does not exist in this address area.
ABSOLUTE MAXIMUM RATINGS
PARAMETER SYMBOL RATING UNIT
Supply voltage Input voltage Output voltage Operating temperature Storage temperature
VCC VIN VOUT Topr Tstg
- 0.3 to +7.0 - 0.3 to VCC + 0.3 - 0.3 to VCC + 0.3 0 to +70 - 65 to +150
V V V C C
RECOMMENDED OPERATING CONDITIONS (TA = 0C to +70C)
PARAMETER SYMBOL MIN. TYP. MAX. UNIT
Supply voltage
VCC
4.5
5.0
5.5
V
DC CHARACTERISTICS (VCC = 5 V 10%, TA = 0C to +70C)
PARAMETER SYMBOL CONDITIONS MIN. MAX. UNIT NOTE
Input `High' voltage Input `Low' voltage Output `High' voltage Output `Low' voltage Input leakage current Output leakage current Operating current Standby current Input capacitance Output capacitance
V IH VIL VOH VOL | ILI | | ILO | ICC1 ICC2 ISB1 ISB2 CIN COUT
I OH = -400 A I OL = 2.0 mA V IN = 0 V to VCC V OUT = 0 V to VCC t RC = 150 ns t RC = 1 s CE = VIH CE = VCC - 0.2 V f = 1 MHz T A = 25C
2.2 - 0.3 2.4
VCC + 0.3 0.8 0.4 10 10 80 70 3 300 10 10
V V V V A A mA mA A pF pF 1 2
NOTES: 1. CE/OE = VIH 2. VIN = VIH or VIL, CE = VIL, outputs open
5-309
LH5324P00A
PRELIMINARY
CMOS 24M Mask-Programmable ROM
AC CHARACTERISTICS (VCC = 5 V 10%, TA = 0C to +70C)
PARAMETER SYMBOL MIN. MAX. UNIT NOTE
Read cycle time Address access time Chip enable access time Output enable delay time Output hold time CE to output in High-Z OE to output in High-Z
tRC tAA tACE tOE tOH tCHZ tOHZ
120 120 120 60 5 50 50
ns ns ns ns ns ns ns
1
NOTE: 1. This is the time required for the outputs to become high-impedance.
AC TEST CONDITIONS
PARAMETER RATING
Input voltage amplitude Input rise/fall time Input reference level Output reference level Output load condition
0.4 V to 2.6 V 10 ns 1.5 V 1.5 V 1TTL + 100 pF
CAUTION
To stabilize the power supply, it is recommended that a high-frequency bypass capacitor be connected between the VCC pin and the GND pin.
5-310
CMOS 24M Mask-Programmable ROM
PRELIMINARY
LH5324P00A
tRC
A-1 - A20 tAA (NOTE) CE tACE (NOTE) OE tOE (NOTE) tOHZ tOH tCHZ
D0 - D7 NOTE: The output data becomes valid when the last intervals, tAA, tACE, or tOE, have concluded.
DATA VALID
5324P00A-3
Figure 3. Byte Mode (BYTE = VIL)
tRC
A0 - A20 tAA (NOTE) CE tACE (NOTE) OE tOE (NOTE) tOHZ tOH tCHZ
D0 - D15 NOTE: The output data becomes valid when the last intervals, tAA, tACE, or tOE, have concluded.
DATA VALID
5324P00A-4
Figure 4. Word Mode (BYTE = VIH)
5-311
LH5324P00A
PRELIMINARY
CMOS 24M Mask-Programmable ROM
PACKAGE DIAGRAM
44SOP (SOP044-P-0600)
1.27 [0.050] TYP.
0.50 [0.020] 0.30 [0.012]
44
23
13.40 [0.528] 13.00 [0.512]
16.40 [0.646] 15.60 [0.614]
14.40 [0.567]
1 28.40 [1.118] 28.00 [1.102]
22
SEE DETAIL 0.20 [0.008] 0.10 [0.004] 2.9 [0.114] 2.5 [0.098]
DETAIL
0.15 [0.006] 1.275 [0.050] 2.9 [0.114] 2.5 [0.098] 0.25 [0.010] 0.05 [0.002] 1.275 [0.050] DIMENSIONS IN MM [INCHES] MAXIMUM LIMIT MINIMUM LIMIT 3.25 [0.128] 2.45 [0.096] 0.25 [0.010] 0.05 [0.002]
1.275 [0.050]
0 - 10 0.80 [0.031]
44SOP
44-pin, 600-mil SOP
ORDERING INFORMATION
LH5324P00A Device Type N Package
44-pin, 600-mil SOP (SOP044-P-0600) CMOS 24M (3M x 8 or 1.5M x 16) Mask-Programmable ROM
Example: LH5324P00AN (CMOS 24M (3M x 8 or 1.5M x 16) Mask-Programmable ROM, 44-pin, 600-mil SOP)
5324P00A-5
5-312

▲Up To Search▲

Price & Availability of LH5324P00A

	To Download LH5324P00A Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .